Mark B. Sawyer
Embedded Systems Developer
Greater Detroit Area
Resume for Mark B. Sawyer ("The Book")
Analytical firmware engineer with extensive experience developing embedded systems
including: handhelds, MP3 players, mid-sized portables (laptops & tablets), and
high end consumer appliances in various industries. Major strengths in all phases
of development including: product definition, architecture & specification,
design & development, new hardware bring-up, hardware, firmware & application
software integration and debug, final test, regulatory certification and release
to production. Additional skills in embedded systems power management encompassing
all levels from high level system chipset and power plane control to low level
battery monitoring and charging. Enthusiastic individual who has ability to function
at all levels of project and product ownership and development, and is comfortable
with sole ownership of project from conception through delivery, as individual
contributor or as member of larger team.
Extensive programming experience in C, C++ and assembler.
Design and development of FORD SYNC Infotainment systems.
- Charter member of newly formed Ford Motor Company in-house Infotainment firmware development group.
- Responsible for adaptations to Ford SYNC3 QNX OS firmware.
- Major area of involvement focused on becoming team subject matter expert for SYNC3 QNX screen and display driver development.
New product design and development of consumer appliances.
- Developed firmware for a Vertical (axis) Machine Wash Appliance Control Unit (VMW).
Developed Class-B (safety related) software and drove regulatory software certification.
Provided factory support for this volume production appliance.
Responsible for release to production of approximately 100 models (variants).
Model differentiation accomplished via parameterization driven by configuration files.
Patent participant in innovative motor braking algorithm to address demands of high volume production.
- Developed firmware for a next generation large capacity Vertical Machine Washer (VMAX).
Developed Appliance Programming Language (APL) Capabilities to support wash cycle
development using Whirlpool proprietary tools and technology created for appliance cycle generation.
Developed appliance parameterization using Whirlpool proprietary Global EE prom (GEE) tool chain.
Developed code to handle requirements of displaying wash cycle Estimated Time Remaining
(ETR) resulting from additional complexities due to cycle engine internals.
Employed learnings from
The Checklist Manifesto to provide coordinated and error free releases of GEE & APL
- Developed firmware for a production upgrade to a Horizontal Axis Washer (ML2016).
Coalesced multiple model lines to single codebase facilitating firmware maintenance
and ensuring performance and feature compatibility between model lines.
Implemented model line improvements (new features and performance upgrades).
Implemented water detection algorithm enabling differentiation between no water
due to a turned off water valve and a non-functional water pressure sensor.
On time release of multiple models to manufacturing.
- Developed firmware for a next generation large capacity Horizontal Machine Washer (AMAX).
Developed Appliance Programming Language (APL) Capabilities to support wash cycle development.
Developed appliance parameterization using proprietary Global EE prom (GEE) tool chain.
Parameter driven architecture taken to the next level resulting in increased efficiencies
for wash cycle development. (Reduced cycle engine footprint.)
Owned and operated custom picture framing franchise.
Responsible for all aspects of this retail operation:
custom framing design and production,
marketing and advertising,
customer and vendor relations,
and all aspects of day to day operations.
(Formerly dba Sawyer Software Solutions, LLC)
Provided consulting services for firmware and hardware design and
development of embedded systems.
- Designed a CDROM embedded controller board based on the Atmel AT89S51 (8051)
microprocessor. This device was a proof of concept and reference design for use in
"music on demand" kiosk applications utilizing standard CDROM drives communicating
via the ATA/ATAPI protocol.
- Responsibilities included hardware and firmware specification and development.
- Hardware development responsibilities included schematic design, board layout,
PCB fabrication and hardware debug.
- Wrote the firmware in 'C' utilizing the "Small Device 'C' Compiler" (SDCC).
- Provided consulting services for the development of a "Blind Spot Alert Sensor"
(BSAS) device based on the Atmel ATMega-8 microprocessor and an infrared (IR) sensor.
The BSAS device was targeted for use in the automotive industry.
- Developed the alert architecture and sensor detection algorithm, wrote the
firmware in assembler and performed initial hardware debug.
- Performed hardware development of a second generation of this design including
schematic entry, board layout, PCB fabrication and hardware debug.
- Provided consulting services to high tech startup specializing in ARM-based ASIC's
providing real time music encoding/decoding and peripheral I/O control.
Developed firmware in C++ and ARM assembler to run on RTXC operating system.
- Principal contributor in the development of PowerManager and Instant-ON
architectures for handheld MP3 players (aka: Portable Juke Box).
- Wrote the firmware for the PowerManager, the InstantON Manager and the
InstantON device handler for the disk subsystem.
- The primary responsibility of the PowerManager was to monitor system
activity in order to detect the system idle condition. When the system idle
condition was detected, the PowerManager provided the high level coordination
required to transition the system into a low-power standby state.
- The Instant-ON architecture consisted of a Manager and power aware drivers
and devices. The Instant-ON Manager maintained a registry of Instant-ON capable
devices and coordinated device entry to and exit from low-power standby
- When in low-power standby, devices were turned off (when possible) and
system clocks were stopped, SDRAM was put into self-refresh and the processor
was switched to a 32KHZ clock and halted. Exit from low-power standby was via
keypad or button activity, USB cable detect or RTC alarm.
- Developed C3 Decoder for CDROM "Yellow Book" Data-CD. This decoder was
responsible for decoding the raw serial data stream from the CD-drive, including:
sync byte detection, descrambling, Error Correction Code (ECC) (S0/S1 syndrome
generation) and Error Detection Code (EDC) (32-bit CRC) processing. The resulting C3
Decoder written in ARM assembler provided a 5X performance improvement over the
equivalent C-language based decoder.
- Developed CDROM Read/Write interface routines for third party (Oak Technology)
Redbook music CD playback utilizing IDE/ATA/ATAPI interface.
- Developed low-level assembler routines for improved hard disk performance for
PIO and DMA modes for IDE/ATA/ATAPI interface.
- Provided consulting services for refinement of IDE/ATA/ATAPI device reset,
identification and initialization.
- Developed performance test for IDE/ATA interface throughput evaluation.
- Provided consulting services to large communications company struggling to resolve
BIOS (General Software) and hardware related problems prior to releasing new product to
manufacturing. Acted as this company's private consultant and liaison to the contracted
New product design and development of internet
appliance systems. Responsibilities and involvement encompassed all phases of the design
process, including initial architecture, design, development, implementation, system
integration and test.
- Participated in all development phases of IAN's WebPAD™ Internet appliance.
This was a redesign of the National Semiconductor WebPAD™ with several product
- Wrote the Embedded Controller Specification during the product definition
- Primary responsibility was the embedded controller firmware architecture, design
and development. The embedded controller (EC) was a National Semiconductor COP8CBR9
microcontroller. The COP8CBR9 incorporated 32k FLASH memory technology, had 14
channels of 10-bit A/D onboard and dual-clock operation. The EC controlled system
power planes, battery charging, display contrast/brightness PWM's and system LED's.
The EC monitored battery status (voltage and current), ACIN status, system thermals,
bezel buttons and touchscreen. EC firmware enhancements over the original National
WebPAD™ design were battery gas-gauge support (utilizing coulomb-counting),
monitoring of several battery/charger error conditions for improved safety, field
upgradability of the FLASH memory via custom bootblock, emulation of NVRAM,
Real-Time-Clock (RTC) emulation, and support for system SUSPEND. All communication
with the host processor was accomplished via Serial Peripheral Interface (SPI). All
code was written in assembler using National's COP8 development tools.
- Also some exposure to National's Geode processors (GXm & GX1), 5530
Companion Chip, Virtual System Architecture (VSA I & VSA II) and ExpressROM
New product design and development of portable laptop
and internet appliance systems. Responsibilities and involvement encompassed all phases of
the design process, including initial architecture, design, development, implementation,
system integration and test.
- Participated in all development phases of a portable laptop system for a major OEM.
- Wrote the BIOS Requirements Document (BRD) and Embedded Controller Specification
during the product definition phase.
- Primary responsibility was the keyboard/embedded controller firmware
architecture, design and development. The embedded controller (EC) was a National
Semiconductor PC87570 Keyboard and Power Management Controller. The firmware was an
adaptation of the Phoenix Multikey Keyboard Controller firmware and was
ACPI-compliant. The EC controlled system power planes, system fan, battery charging,
display contrast/brightness PWM's and system LED's. The EC monitored battery status
via SMBUS (Smart Battery) protocol. The EC performed power button management
providing momentary and 4-second override functions. The EC monitored ACIN, modem
RING and HOTKEY events. The EC provided support for system SUSPEND. All code was
written in assembler using National's CR16 development tools.
- Participated in all development phases of the productization of National's
WebPAD™ internet appliance.
- Wrote the Embedded Controller Specification during the product definition
- Primary responsibility was the embedded controller firmware architecture, design
and development. The embedded controller (EC) was a National Semiconductor COP8SGE7
microcontroller. The EC controlled system power planes, battery charging, display
contrast/brightness PWM's and system LED's. The EC monitored battery status (voltage
and current), ACIN status, system thermals, bezel buttons and touchscreen. All
communication with the host processor was accomplished via a custom, nibble-wide
Host I/F Bus. All code was written in assembler using National's COP8 development
Provided consulting services for firmware and software design and
development of microprocessor-based notebook and embedded systems.
- Participated in all phases of ROM BIOS development of two major OEM Pentium and
80486SL based notebook products. Principal contributor and architect during
development and implementation of power-management and System ROM BIOS firmware.
Familiar with PicoPower Redwood, Fir, Golden Gate and Vesuvius, and Intel 82360SL,
Western Digital WD8110 chipsets, ESS 688, 968, 1488, 1688 and 1868 sound chips,
Pentium and 80486SL power-management features, SMM and SMI handler code and versions
1.0 - 1.2 of the Intel/Microsoft Advanced Power Management Interface (APMI)
Specification. All code written in assembler.
- Performed low-level ROM BIOS, SMM, SMI and APMI debugging of a pen-based
notebook using HICE-486SL, Soft-ICE and Soft-ICE for Windows.
- Developed ROM BIOS POST and initialization code for Phoenix 38802 MultiKey
- Principal contributor to adaptation of MISER to Redwood chipset.
Involvement included development of SMI dispatcher, Suspend/Resume code and keyboard
- Performed low-level ROM BIOS, SMM and SMI debugging of Redwood chipset using
Tektronics DAS and Soft-ICE.
- Developed MISER and APMI code to implement:
- FailSafe timer for Suspend support
- Resume on Modem Ring and Resume on Calendar Event
- AutoFast CPU clock slow-down and speed-up
- StopGrant CPU clock stop-on-halt
- Was principal contributor to integration of pen/digitizer hardware support to
ROM BIOS and MISER.
- Developed ROM BIOS initialization and management code for an external L2
- Was principal contributor and architect of power-management firmware for a
high-end Pentium based notebook. Responsible for design and development of SMM code
to support Suspend/Resume, Global Standby, local device power-management, APM, and
- Provided software support to a Z80 microprocessor based Power Monitor/Control System
(IMPRESS). IMPRESS was a real-time, event-driven, data acquisition and process control
system designed specifically for managing telephone office central power room resources.
IMPRESS I/O consisted of 12-bit ADC's, binary logic input channels, relays, LED's,
audible alarms and remote alarm notification via modem. IMPRESS supported both local and
remote (modem) secured access for two simultaneous users, provided energy management of
the rectifiers under its control and was capable of generating system load statistics.
Two levels of password controlled access were supported with read-only or read/write
privileges and a Call Back Security option (via modem) for installations where remote,
secured access was required. IMPRESS was housed in a single rack mounted chassis and
used the STD-BUS industrial microcomputer bus standard. All code (32k bytes) written in
New product software design and development of
networked desktop and workstation systems encompassing all phases of the
design process, including initial design, development, implementation, system integration
- As a member of the Distributed Processing Engineering group, developed code for DEC's
Universally Unique Identifier (UUID), Cell Directory Service (CDS) and Remote
Procedure Call (RPC) products. These products became part of OSF's Distributed
Computing Environment (DCE). All code written in 'C' and developed on Ultrix.
- Designed the initial implementation of DEC's UUID architecture. UUID's are
Universally Unique IDentifiers used widely in DEC's networking and distributed
processing environments. Algorithms based on the current time and the local ethernet
address were employed to guarantee the uniqueness of each UUID created. Implemented
on DEC's Ultrix operating system, BSD sockets and U*ix IOCTL function calls were
used to ascertain the ethernet address. Functions implemented supported UUID
creation, lexical comparisons and string and binary conversions.
- Participated in the initial RPC team formation and defining of project and
product goals. This evolved into a joint development project with HP/Apollo using
Apollo's NCS as a base. The resulting RPC product was submitted to OSF and became
part of OSF/1's Distributed Computing Environment (DCE).
- Provided technical support to the development of the common code for the DEC and
HP/Apollo RPC joint development project. This code was common to both the UDP/IP
(connection-less datagram) and TCP/IP (connection-full) RPC transport protocols.
Designed, implemented and tested portions of the common code as part of the
- Designed and implemented the initial RPC connection based network receiver,
secondary address and Auto-Start code.
- Developed the TCP/IP connection oriented receiver code. Data received and
processed by this code was passed to the RPC common code for scheduling and
dispatching. Network code used the BSD socket interface and U*ix IOCTL function
- Developed the connection based secondary address code. This code was
responsible for receiving incoming (client) connection requests at the TCP/IP
well-known port address and acquisition of a secondary address for subsequent
client/server communications. This was done in order to free up the well-known
port for future incoming client requests.
- Developed the connection based auto-start code. This code (in concert with
the receiver code) was responsible for handling server auto-start requests
initiated by the U*ix daemon inetd. The primary difference here was that the
server standard input and output were redirected to the network socket. The BSD
socket interface and U*ix IOCTL function calls were used to determine the
- Converted the CDS control program (CDSCP) management functions from NCL to an RPC
based protocol, designed and implemented the CDS Cached Server functionality and
participated in various phases of testing (component, functional, system and
- Converted the CDS control program (CDSCP) from DEC's proprietary Network
Control Language (NCL) to RPC. This involved rewriting all of the CDS management
functions to use RPC function calls instead of NCL protocols. Modifications were
made to the CDS control program, server and advertiser modules.
- Developed the CDS Cached Server functionality. This code facilitated
nameserver startup and initialization in WAN environments where no local
nameservers were accessible via the normal datagram LAN broadcast algorithm. The
cached server functionality provided system and namespace administrators with
the ability to define, delete and view cached server information in the
namespace. Modifications were made to the CDS control program, server and
- Developed the CDS clearinghouse functionality. This code provided system and
namespace administrators with the ability to view local and remote nameserver
clearinghouse information. Modifications were made to the CDS control program,
server and advertiser modules.
- Provided technical support to CDS testing in the form of component,
functional, system and stress testing. This testing took the form of component
black box functional testing, white box routine specific testing, multi-platform
system interoperability testing and component and system stress testing. Test
scripts were written in the Bourne Shell making extensive use of CDSCP and the
U*ix utilities awk, grep, sed and perl.
- Provided technical support to CDS defect resolution (i.e. bug-fixes). This
support encompassed all components of the CDS (control program, advertiser,
server, and clerk). CDS defects were tracked with OSF's Open Track defect
tracking system. CDS source code was maintained and developed using OSF's
- Provided support to OSF's integration efforts for OSF/1 DCE.
- Provided technical support to CDS testing during OSF system integration.
This involved working with OSF personnel in the form of telephone support and
visits to OSF.
- Presented a technical lecture and overview of the design, implementation and
test of CDSCP for OSF.
- As a member of the PC Systems Group, developed MS/DOS device driver and operating
system code for the DEC VAXmate, an IBM/AT compatible. All code written in 'C' and
- Added Microsoft Version 6 mouse driver functionality to DEC's Logitech mouse
driver. This involved the research and specification of the details of the
additional functionality and the implementation and test of the version 6 compatible
- Provided technical support to the development of the VAXmate, an 80286 based
- Responsibilities included making modifications to and testing of DOS
utilities (SYS, CHKDSK, DISKCOMP and DISKCOPY), incorporating functional
improvements specific to DEC's release of Microsoft's V3.xx DOS and PCSA.
- Provided support to test and development of DEC's LK250 keyboard. Support
consisted of testing for compatibility with IBM's standard keyboard and support
to the development of the LK250 microprocessor (8051) firmware when
compatibility bugs were found.
- Provided technical support to a special development effort of DEC's VAXmate
Int13h ROM BIOS services undertaken to address copyright issues.
- Provided technical support to the development of the PandaMate, an 80386 based
PC. Acted as a technical liaison to Phoenix Technology during the specification of
the [Phoenix] ROM BIOS. This included incorporation of Network boot capability for a
diskless configuration and ROM BIOS support for the PandaMate SCSI
- Provided technical support to the investigation of implementing RPC on MS/DOS.
Responsibilities included familiarization with the RPC paradigm, techniques and
design and architectural concerns. Familiarization with DEC's initial VAXrpc
implementation and subsequent DECrpc architecture. Investigated requirements of
implementing the DECrpc architecture on DEC's PC's.
Provided consulting services for firmware and hardware design and
development of microprocessor based systems.
- Performed evaluation of the ROM BIOS firmware for the DEC VAXmate, an IBM/AT
compatible. Evaluation included extensive functional and IBM/AT compatibility testing of
the ROM BIOS video, keyboard, memory and disk services. Testing resulted in a product
that was not only functionally equivalent but also bug-for-bug compatible with the
IBM/AT. All code written in 'C' and 80x86 assembler.
- Ported a Z8 microprocessor hardware and firmware design to a new product. This design
was an option board in a Hayes compatible modem providing X.25 network communications
capabilities. All code written in assembler.
- Performed the hardware design and provided support to the layout of the option
- Ported the original firmware design to the new product. This included the
removal of the original asynchronous capability and the addition of a special option
board interface to replace the original Hayes AT command interface.
- Performed Telnet certification of this product before its release to the
customer. This necessitated modifications to the level 2 (HDLC) and level 3 protocol
layers to meet Telnet X.25 requirements.
- Principal contributor to the firmware and software design and development of an
IBM/PC compatible BIOS and MS/DOS compatible Run-Time-System for a hand-held computer.
All code written in 80x86 assembler. Principal contributor to the software
design and development of the application code to use this computer as an inventory
calculator. Application code written in Lattice-C and 80x86 assembler.
- Developed a superset of the IBM ROM BIOS compatible Int14h RS-232 serial
communications services. This implementation provided buffered, interrupt-driven
transmit and receive capability.
- Developed the power-fail NMI handler for this battery powered product.
- Developed Run-Time Logging functionality to facilitate both hardware and
software debugging of the application and run-time systems. This feature was
intended to be used primarily during postmortems of failed units returned from the
- Developed several different program and data file memory loaders for this RAM and
ROM based product.
- ASCII bootstrap debugger/loader (Inspect & Change) implemented and used
extensively during early product development.
- Intel HEX loader implemented for loading early prototype code.
- Pure binary loader implemented for loading the basic operating system during
- MS/DOS .EXE and .COM file loader implemented to support product development
using standard MS/DOS language tools.
- 'Total memory clone' loader implemented to support replication of fully
configured inventory calculators.
- Detailed design documentation was provided to the customer for various aspects
of the implementation.
- Principal contributor to the development effort of the application software
for this handheld product that enabled this computer to be used as a multi-mode
inventory calculator. Product capabilities included collection and analysis of
- In SKU Mode (Stock Keeping Unit), this handheld unit was used by personnel
engaged in collecting inventory statistics.
- In Financial Mode, this handheld unit was used as an inventory calculator
providing store managers with the ability to analyze inventories on a
- Follow-on work involved making modifications to the base inventory calculator
product application software to accommodate special customer (Payless/Target)
requests and development of productivity enhancement tools used during product
- Modifications to the application software to accommodate automated loading
of special customization and parameterization data.
- Modifications to the low-level 'C' runtime library memory management
routines to accommodate special requirements related to loading calculator
customization and parameterization data. The data loaded became a permanent part
of the application program image.
- Implemented a makefile preprocessor to facilitate product builds.
Preprocessor directives were embedded in a master makefile containing all
information necessary to build all variations of the product. The preprocessor
was used to prepare makefiles specific to a particular product target using
selectable build tools.
- Implemented optimized assembler versions of Plessy and Fix39 barcode
decoders originally implemented in 'C'.
- Designed and implemented a barcode decoder test suite (DTS). The DTS
facilitated development and test of new barcode reader decoder algorithms.
Prototype decoder modules containing new algorithms were linked with the DTS
executable and called by the DTS with raw barcode data previously obtained and
preprocessed by the DTS. The DTS verified new decoders for correctness and
measured performance characteristics.
- Ported an IBM/PC serial communications package to the DEC Rainbow. This port
consisted of modifying code using the IBM/PC ROM BIOS services to instead use
the Rainbow MS/DOS IOCTL services.
Provided consulting services for firmware and software design and
development of microprocessor based systems. All programming done in assembly language.
- Principal contributor to various operating system and product ports including
installation of GWBASIC, MS/DOS V2.11 and CP/M-80 V2.2 on new products. This involved
writing the OEM dependent BIOS firmware and/or software support for the OEM hardware,
initial system integration and hardware debug.
- Installation of GWBASIC on two IBM clones. This involved
writing the OEM dependent software interfacing with the OEM hardware and general
support to debug and test. Primary responsibilities included writing the software
supporting the GWBASIC donote SOUND and PLAY statements and the serial
communications routines. Serial communications were fully buffered and interrupt
driven for both transmit and receive.
- Installation of MS/DOS V2.11 on an 80C86 based product. This
involved writing the OEM BIOS firmware as well as initial system integration and
hardware debug. Primary firmware responsibilities included development of the
communications device driver.
- Installation of CP/M-80 V2.2 on an 8088/Z80 multiprocessor
designed product. This involved writing the OEM BIOS software, system integration
and hardware debug. Primary responsibilities included writing BIOS support for video
display escape sequence processing and CP/M reader and punch serial communications
- Participated in the development of diagnostics for a 68000 based network file
server. A menu driven user interface was implemented with various levels of diagnostics.
Diagnostics were capable of different levels of error reporting with messages
appropriate for the operator's level of expertise and the level of diagnostics
requested. Primary responsibilities included writing the memory tests for this segmented
and paged memory implementation and writing the printer tests for this Centronics
compatible custom printer I/O implementation.
Microprocessor hardware and software design and
development of dot matrix printers. Experience included specification, design, development
and testing of embedded controllers in multiprocessor controlled printers.
- Firmware design experience included writing stepper motor driver and operating
system kernel firmware for high performance multiprocessor controlled printers.
- Hardware design experience included design and implementation of an 8088
microprocessor based front-end in a multiprocessor controlled printer. Firmware
development the hardware design effort included development of the ROM diagnostics and
of the printer front-end operating system kernel firmware.
- As lead engineer, provided technical support and guidance to Associate Engineer
developing LCD controller firmware.
- Other tasks included system management of the Engineering PDP 11/34, development of
RSTS/E support utilities and technical support to a proposal for a CAD system for dot
matrix character set development and generation.
Responsibilities included hardware and software design and development on
military Fire Control Systems. As lead engineer responsibilities included task management
and supervision of Associate Engineers. As design, engineer responsibilities included
hardware and software design and development of microprocessor based systems.
- Participated in the initial power-up and diagnostic checkout of the first AEGIS
Switch Converter Cabinet (SCC) and Data Converter Cabinet (DCC) hardware. This involved
the orderly installation, power-up and hardware and software checkout of each cabinet
subsystem. The various subsystems incorporated many different types of converters,
(analog to digital, digital to analog, synchro to digital, digital to synchro), logic
input and output channels and analog power amplifiers.
- Principal contributor to the AEGIS Converter Computer Evaluation and
Performance Test (ACCEPT) program. ACCEPT was written in CMS-2 and assembler and
executed on a UYK-20. ACCEPT was used during the initial power-up and diagnostic
checkout of the AEGIS SCC and DCC, was used to perform the final AEGIS performance and
qualification testing by the Navy, was used to exercise the SCC and DCC cabinets during
EMI testing and evaluation and ultimately became the factory acceptance test used in
- Designed hardware and logic for an NTDS I/O computer buss adapter card. This
design employed state machines embodied in an 82S105 FPLS. The buss adapter responded to
computer I/O requests and controlled the flow of information to the NTDS I/O
- Principal contributor for Guided Missile Launcher System (GMLS) simulator
firmware for a training system used by the German navy. This firmware (and associated
control cabinet) interfaced with a missile launcher and simulated many of the functions
available in a fully operational fire control system. All code written in assembler. Was
a principal contributor during the initial power-up and checkout of the training system
and acceptance test and performed the installation and checkout in Germany.
- Designed hardware and firmware for a 6802 microprocessor based
digital cassette tape controller. This design provided an RS-232 interface to a digital
cassette tape transport mechanism. All code written in 6802 assembler.
- Received a Bachelor of Science in Electrical Engineering (BSEE), Cum Laude,
from the University of New Hampshire, 1977.
Life member of Tau Beta Pi Engineering Honor Society.
- Dynamic Resource Allocation Across Bus Bridges
- Motor Braking: Method and apparatus to electronically stop washing machine basket
ATMega-8, AT89S51 (8051)
Pentium, 80486, 80386, 80286, 8088, 8086, 8080, 8085, 8048, 8049, 8051
PC87570 (CR16), COP8, Geode (GXm, GX1)
C, C++, Python, Forth, Pascal, Fortran, CMS-2, Perl, PLM/86, Basic
Most of the above processors.
QNX, Whirlpool Vortex, RTXC RTOS, Win-2K, Win-9x, Win-3.x, WFWG, MS/DOS, Linux, Unix, Ultrix, OSF/1,
DCE, CPM, VAX VMS, ISIS
QNX Momentics, Eclipse, SVN, Lattix, IAR Workbench, SDCC, Atmel AVR, ARM, Microsoft, AsmCOP, Intel, Phoenix, Lattice,
CR16, Tektronics, Periscope, MicroBench, Microtec, Zilog, American Arium, OSF ODE,
2500AD, Soft-ICE, Digital Research, MetaLink, PVCS
Copyright © 2010 - 2017, Mark B. Sawyer, All rights reserved.
This document may not be modified without prior written permission.